The present invention relates to semiconductor integrated circuit, and moreover to technology which is effective when adopted to a composite logic circuit consisting of CMOS device and bipolar transistor. It is also directed to technology which is effective when adopted, for example to an arithmetic operation circuit forming the arithmetic operation logic unit of microcomputer.
As a logic gate circuit which requires larger load driving force than that of CMOS (complementary MOS) circuit and less power consumption than that of bipolar logic circuit, a composite logic gate circuit (hereinafter called a Bi-CMOS logic circuit) as indicated in FIG. 4 has been proposed (e.g., see Nikkei Electronics, from page 188 to page 189, issued on Aug. 12, 1985, Nikkei Mcgrowhill), in which the output part is formed by a totem pole type buffer consisting of bipolar transistors Q.sub.5, Q.sub.6 and the input logic part LG which controls such an output part is formed by P-MOSQ.sub.1, Q.sub.2 and N-MOSQ.sub.3, Q.sub.4.
Said Bi-CMOS logic circuit is capable of sufficiently utilizing the advantages in high speed operation and low power consumption in case it is adopted to an input/output buffer, a bus driver and a clock driver, etc. having a large load.